How many entries are in the page table

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Please ask a specific question. Add a comment. Active Oldest Votes. I hope this may help Improve this answer. Maharaj Maharaj 3 3 silver badges 17 17 bronze badges. So instead of 38 bits I would use the first result of 16 bits both in section 3 and 4. And now I understand section 5! I have updated my post accordingly. Sign up or log in Sign up using Google. Sign up using Facebook. Sign up using Email and Password. Post as a guest Name. Anderson Craig S. Anderson 6, 4 4 gold badges 28 28 silver badges 43 43 bronze badges.

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Podcast Do polyglots have an edge when it comes to mastering programming Featured on Meta. Now live: A fully responsive profile. Related Hot Network Questions. A good exercise is to work out all of the above computations with small numbers, and to actually fill out the contents of RAM on a piece of paper. For example, you could try designing everything with a page size of 8 bytes, a physical address space of bytes, and a logical address space of bytes.

Figure out how to look up address 0x3A. Roll a of frames -sided die whenever you need to find a frame for a page. Here is a blank sheet of RAM ; you would only use half of it for the scenario above since the physical address space is , not You could also print out lots of pages and experiment with a page size of bytes. The size of the page table hierarchical or otherwise grows with the size of the virtual address space.

If we have a large virtual address space such as in a 64 bit architecture , the page table will become huge. Hierarchical paging will allow us to keep most of that out of main memory, but would require a 6-level hierarchy why?

That means to look up an address you need to read at least 6 frame numbers, which is expensive. Instead of making a very large sparse array, we can instead use a hash table with one entry per frame.

The hash table maps page numbers to frame numbers. How does the MMU actually work with these fancy paging schemes? The key component is the translation lookaside buffer TLB. The TLB is a small hardware associative array think tens to hundreds of entries that maps page numbers to frame numbers.

As the program executes, the page numbers stored in virtual addresses are compared with all of the entries in the TLB this is done in hardware, so all comparisons can happen simultaneously. If an entry matches, the corresponding frame number is combined with the offset to give the physical address.

If no entry matches, there is a TLB miss. If using a software-managed TLB , this miss will cause an exception to be raised; the operating system is then responsible for traversing the page tables to find the corresponding frame; it then loads the mapping into the TLB and continues. If using a hardware-managed TLB , the TLB is responsible for traversing the page table structure; it only raises an exception if the page table has not yet been properly configured.

Recall that each process has its own address space, and thus its own page table. This means that when the OS context switches to a new process, it switches the pointer to the root of the page table to a the page table for the new process this is the "VM info" stored in the PCB referred to in the first week.